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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd16707a 263/256-output tft-lcd gate driver data sheet document no. s16563ej1v0ds00 (1st edition) date published january 2004 ns cp (k) printed in japan 2003 the mark shows major revised points. description the pd16707a is a tft-lcd gate driver equipped with 263/256- output lines. it can output a high-gate scanning voltage in response to cmos level input because it provided with a level-shift circuit inside the ic circuit. it can also drive the xga /sxga/ sxga+, and since the input signal is placed symmetr ically, this product can wire easily between gate drivers. features ? cmos level input (2.3 to 3.6 v) ? 263/256 outputs ? high-output voltage (v dd2 to v ee : 40 v max.) ? capable of all-on outputting (/aor, /aol) ? input terminal symmetrical placement ? adapted to tcp/cof remark /xxx indicates active low signal. ordering information part number package pd16707an-xxx tcp (tab package) pd16707anl-xxx cof remark purchasing the above chip entail t he exchange of documents such as a separate memorandum or product quality, and the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives.
data sheet s16563ej1v0ds 2 pd16707a 1. block diagram ls2 note ls2 note ls2 note ls2 note ls2 note ls2 note 263-bit shift register sr1 sr263 sr262 sr261 sr3 sr2 r,/lr o 263 o 262 o 261 o 3 o 2 o 1 v ee /aor oer stvr clkr stvl mode clkl oel /aol o 0 o 264 v ee level v ee level r,/ll note ls2: shifts cmos level and output level (v dd2 to v ee ).
data sheet s16563ej1v0ds 3 pd16707a 2. pin configuration ( pd16707an-xxx: tcp) (copper foil surface, face-up) ic view ? direction v dd2 v dd2 v dd1 v dd1 oel o 264 o 263 o 262 o 261 clkl v ee v ee v ss v ss mode stvl r,/ll /aol o 3 o 2 o 1 o 0 v dd2 v dd2 v dd1 v dd1 oer clkr v ee v ee v ss v ss stvr r,/lr /aor chip back side remark this figure does not s pecify the tcp package.
data sheet s16563ej1v0ds 4 pd16707a 3. pin functions pin symbol pin name i/o description o 1 to o 263 driver output these pins output scan signals that dr ive the vertical direction (gate lines) of a tft-lcd. the output signals change in synchronization with the rising edge of shift clock clk. the driver output amplitude is v dd2 -v ee . o 0 , o 264 driver output the signal of v ee level is outputted by fixation. r,/lr, r,/ll shift direction control input the shift direction control pin of shift register. r,/lr, r,/ll = h (right shift): stvr o 1 o 263 stvl r,/lr, r,/ll = l (left shift): stvl o 263 o 1 stvr r,/lr and r,/ll are connected inside ic. stvr, stvl start pulse i/o this is the i/o of the internal shift r egister. the start pulse is read at the rising edge of shift clock clk (clkr, clkl), and scan signals are output from the driver output pins. the input level is a v dd1 -v ss (logic level). when in mode = h, the start pulse is output at the falling edge of the 263rd clock of shift clock clk, and is cleared at the falling edge of the 264th clock. the output level is v dd1 -v ss (logic level). clkr, clkl shift clock input this pin inputs a shift clock to the in ternal shift register. the shift operation is performed in synchronization with the rising edge of this input. clkr and clkl are connected inside ic. oer, oel output enable input when this pin goes hi gh level, the driver output is fixed to v ee level. the shift register is not cleared. clk is asynchronous in the clock. oer and oel are connected inside ic. /aor, /aol all-on control input when this pin goes low level, all driver output = v dd2 level. the shift register is not cleared. th is pin has priority over oer and oel. this pin is pulled up to v dd1 power supply inside ic. clk is asynchronous in the clock. /aor and /aol are connected inside ic. mode selection of number of outputs input mode = v dd1 or open: 263 outputs mode = v ss : 256 outputs (driver pins o 129 to o 135 are invalid.) input level is v dd1 -v ss (logic level) this pin is pulled up to v dd1 power supply inside ic. v dd1 logic power supply ? 2.3 to 3.6 v v dd2 driver positive power supply ? 5 to 30 v. the driver output: high level v ss logic ground ? connect this pin to the ground of the system. v ee negative power supply for internal operation ? ? 15 to ? 3 v. the driver output: low level cautions 1. to prevent latch-up, turn on power to v dd1 v ee v dd2 logic input in this order. turn off power in the reverse order. these power up/down sequence must be observed also during transition period. 2. insert a capacitor of about 0.1 f between each power line, as shown below, to secure noise margin such as v ih and v il . v dd2 v dd1 v ss 0.1 f 0.1 f 0.1 f v ee
data sheet s16563ej1v0ds 5 pd16707a 4. relations of enable output pin number selection and output pin switching is possible for 263/256 with pd16707a by the mode pin. mode = h or open mode = l 263-output mode 256-output mode o 1 o 1 o 2 o 2 o 3 o 3 o 4 o 4 o 5 o 5 o 6 o 6 o 127 o 127 o 128 o 128 o 129 v out = v ee o 130 v out = v ee o 131 v out = v ee o 132 v out = v ee o 133 v out = v ee o 134 v out = v ee o 135 v out = v ee o 136 o 136 o 137 o 137 o 259 o 259 o 260 o 260 o 261 o 261 o 262 o 262 o 263 o 263
data sheet s16563ej1v0ds 6 pd16707a 5. timing chart (r,/lr = r,/ll = h, mode = h, /aor = /aol = h) clkr 1 oer o 1 (o 263 ) o 2 (o 262 ) stvl (stvr) o 1 of next stage (o 263 of next stage) o 2 of next stage (o 262 of next stage) 2 3 262 263 264 265 stvr (stvl) o 3 (o 261 ) o 262 (o 2 ) o 263 (o 1 ) 266 clkl oel remark the signal name in parenthesis is it at the time of r,/lr = r,/ll = l.
data sheet s16563ej1v0ds 7 pd16707a 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit logic supply voltage v dd1 ? 0.5 to +7.0 v driver positive supply voltage v dd2 ? 0.5 to +32 v power supply voltage v dd2 -v ee ? 0.5 to +42 v internal operation negative supply voltage v ee ?16 to + 0.5 v input voltage v i ? 0.5 to v dd1 + 0.5 v operating ambient temperature t a ? 20 to +75 c storage temperature t stg ? 55 to +125 c caution product qualify may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?20 to +75 c, v ss = 0 v) parameter symbol condition min. typ. max. unit logic supply voltage v dd1 2.3 3.3 3.6 v driver positive supply voltage v dd2 5 20 30 v internal operation negative supply voltage v ee ? 15 ? 5 ? 3 v power supply voltage v dd2 -v ee 8 25 40 v clock frequency f clk 500 khz
data sheet s16563ej1v0ds 8 pd16707a electrical characteristics (t a = ?20 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 20 v, v ee = ?5 v, v ss = 0 v) parameter symbol condition min. typ. note max. unit high level input voltage v ih 0.8 v dd1 v dd1 v low level input voltage v il clkr, clkl, stvr, stvl, r,/lr, r,/ll, oer, oel, mode v ss 0.2 v dd1 v high level output voltage v oh stvr (stvl), i oh = ? 40 a v dd1 ? 0.4 v dd1 v low level output voltage v ol stvr (stvl), i ol = +40 a v ss v ss + 0.4 v lcd driver output on resistance r on v out = v ee + 1.0 v or v dd2 ? 1.0 v 0.4 1.0 k ? pull-up resistance r pu v dd1 = 3.0 v (/aor, /aol, mode) 10 50 100 k ? input leak current i il v i = 0 v or 3.6 v (except for /aor, /aol, mode) 1.0 a static current dissipation i dd1 v dd1 , f clk = 50 khz, oer = oel = l, f stv = 60 hz, no load 20 200 a i dd2 v dd2 , f clk = 50 khz, oer = oel = l, f stv = 60 hz, no load 10 100 a i ee v ee , f clk = 50 khz, oer = oel = l, f stv = 60 hz, no load ?300 ?30 a remark stv: stvr (stvl) note the typ. value are reference values at v dd1 = 3.0 v, t a = 25 c.
data sheet s16563ej1v0ds 9 pd16707a switching characteristics (t a = ?20 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 20 v, v ee = ?5 v, v ss = 0 v) parameter symbol condition min. typ. max. unit cascade output delay time t phl1 c l = 20 pf, 500 ns t plh1 clkr (clkl) stvl (stvr) 500 ns t phl2 500 ns t plh2 c l = 300 pf, clkr (clkl) o n 500 ns t phl3 500 ns driver output delay time t plh3 c l = 300 pf, oer (oel) o n 500 ns output rise time t tlh c l = 300 pf 800 ns output fall time t thl 800 ns input capacitance c i t a = 25 c 15 pf timing requirements (t a = ? 20 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 20 v, v ee = ? 5 v, v ss = 0 v) parameter symbol condition min. typ. max. unit clock pulse high width pw clk(h) 500 ns clock pulse low width pw clk(l) 500 ns enable pulse width pw oe 1000 ns data setup time t setup stvr (stvl) clkr, clkl 200 ns data hold time t hold clkr, clkl stvr (stvl) 200 ns remark unless otherwise specified, the input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 . caution keep the time and fall time of the logic input to t r = t f = 20 ns (10 to 90% of the rated values).
data sheet s16563ej1v0ds 10 pd16707a switching characteristics waveform (r,/lr = r,/ll = h, mode = h) unless otherwise specified, t he input level is defined to be v ih = 0.8 v dd1 , v il = 0.2 v dd1 . t setup clkr stvr t r 90% 10% t hold pw clk(h) t f 1 260 261 2 3 t plh2 o 1 t phl2 o 2 o 262 o 263 t plh1 stvl t phl1 oer t phl3 o 1 to o 263 t plh3 4 5 6 7 262 263 ? 90% 10% t tlh t thl pw oe pw clk(l) 50% 50% 10% 90% 50% 90% 10% 50% 50% clkl oel
data sheet s16563ej1v0ds 11 pd16707a 7. recommended mounting conditions the following conditions must be met of mounting conditions of the pd16707a. for more details, refer to the [semiconductor device mounting manual] (http:// www.n ecel.com/pkg/en/mount/index.html) please consult with our sales offices in case other m ounting process is used, or in case the mounting is done under different conditions. pd16707an-xxx: tcp (tab package) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c: pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s16563ej1v0ds 12 pd16707a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16707a reference documents nec semiconductor device reliability /quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of january 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec ele ctronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the cust omer. nec electronics assu mes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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